module control (
  clk, reset, in, clr, count
);

  input clk, reset, in;
  output reg clr, count;

  parameter S0 = 2'b00;
  parameter S1 = 2'b01;
  parameter S2 = 2'b10;

  reg[1:0] cur_state, nxt_state;

  always @(posedge clk) begin
    if ( reset ) cur_state <= S0;
    else         cur_state <= nxt_state;
  end

  always @(posedge clk) begin
    if ( reset ) nxt_state = S0;
    else begin
      case (cur_state)
        S0  : 
          if ( in ) nxt_state = S1;
        S1  :
          if ( in ) nxt_state = S2;
        S2  :
          if ( in ) nxt_state = S0;
      endcase
    end
  end

  always @(*) begin
    case (cur_state)
      S0  : begin
        clr = 1;
        count=0;
      end
      S1  : begin
        clr=0;
        count=1;
      end 
      S2  : begin
        clr=0;
        count=0;
      end
    endcase
  end

endmodule